With the development of RF circuits, RF devices gain more and more attention in radio communications, for example, personal/commercial radio communication apparatus, mobile communication apparatus and even some important fields such as military radars, etc., and the demands on thereof also increases year by year. In the transceiver systems of a RF circuit, a power amplifier is a very important module. However, a power amplifier is generally required to process a signal with a large amplitude and to have a good stability, which requires that the core elements of the circuits of the power amplifier have a good high voltage-resistant capability. Generally, the core elements of such circuits are manufactured by employing complex processes with expensive special materials or manufactured by employing planar lateral double-diffused field effect transistors (planar LDMOS). Although the planar lateral double-diffused field effect transistor is compatible with the conventional CMOS process, under the background that the improvement of the key processing steps such as lithographying in the CMOS process is limited and the object of batch production via advanced technologies cannot be attained, the structure of the planar transistor causes a continual increase of cost and a reduction of the yield. At present, taking 45 nm flat tube process as an example, the technology has reached the process limit, and a serious short channel effect will be introduced into the flat tube, which results in an increase of the off-state current and a reduction of transconductance in the device. At the same time, since a lateral double-diffused field effect transistor with a planar-structure has a large drain/substrate conjunction reverse bias during the normal operation, a large drain/substrate leakage current exists, which affects the precision of the output current, and the large drain/substrate reverse bias may even result in the device is brokendown soon and thus reduce the high voltage-resistant capability of the LDMOS.
On one hand, silicon nanowire MOS field-effect transistor (Silicon Nanowire MOSFET) may attain an excellent gate control capability, mitigate the short channel effect and overcome the problem that it is difficult for an ordinary planar transistor to reduce the characteristic size of a device. On the other hand, because of the floating channel structure, the effect of no substrate is obtained, and the LDMOS consisted thereby may overcome the problem of large leakage current and quick breakdown in a planar LDMOS.
Therefore, by using the high voltage-resistant lateral double-diffused field effect transistor manufactured based on a nanowire MOS field-effect transistor, a good choice is provided for further improving the integration degree and the performance of an ultra-large scale integrated circuit. Moreover, a good choice is provided for a power amplifier module or other high-voltage circuits requiring a reliable and stable operation.